Dynamic random access memories (DRAMs) dissipate a great deal of energy in the process of charging and discharging the bit lines of the semiconductor memory arrays. This charging and discharging is necessary for the operation of these circuits, but the dissipation of the associated energy causes a drain on the energy supply and increases the thermal energy that must be removed from the semiconductor chip. In battery powered applications, this shortens the time between necessary recharging of the battery. Also, large systems need very large banks of batteries to hold the information in a DRAM in the event of a power failure, or to allow the information to be written into non-volatile storage such as magnetic storage.
A technique for lowering power consumption in computing has been described as adiabatic switching. In adiabatic switching charging and discharging is carried out over longer time periods than the RC time constant of the node being charged so that low voltage drops occur across switches carrying charging current. In a publication by J. G. Koller et al. entitled "Adiabatic Switching, Low Energy Computing and the Physics of Storing and Erasing Information", Workshop on Phys. and Comp. "Phys. Comp. 92", IEEE p. 267 Oct. 2, 1992, an adiabatic AND gate and power supply is shown in FIG. 3 and an Adiabatic latch circuit is shown in FIG. 4.
The application of adiabatic switching and energy recovery to digital CMOS logic to reduce dynamic power dissipation has been described in a publication by W. C. Athas et al. entitled "An Energy-Efficient CMOS Line Driver Using Adiabatic Switching", University of Southern California, Information Sciences Institute, Marina del Ray, Calif. dated Nov. 2, 1993. In the paper, an adiabatic power supply is described consisting of a capacitor, switch and inductor coupled in series for flowing charge through an adiabatic line driver chip onto the load capacitances and back again.
With adiabatic switching, the energy dissipated will be reduced compared to conventional switching with the circuit speed also being reduced to allow circuit nodes to charge at slower rates than the RC time constant of the circuit nodes. In the above publication by W. C. Athas et al. a factor of 6.3 increase in energy efficiency at 1 MHz was obtained.